-- Copyright (c) 2006 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
--
-- This provides a PCA9555 on address 0x26 for the T-Rex C1 board.
-- The high nibble of port 0 are the 4 dip switches and the low nibble are the buttons KEY0 to KEY3.
-- Reset is KEY7.
-- Write to port 1 for updating the 8 LEDs.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity t_rex_test is
	port(
		clock_50mhz: in std_logic;
		scl: in std_logic;
		sda: inout std_logic;
		led: out unsigned(7 downto 0);
		button: in unsigned(3 downto 0);
		dip_switch: in unsigned(3 downto 0);
		neg_reset: in std_logic);
end entity t_rex_test;

architecture rtl of t_rex_test is

	component pca9555 is
		generic(
			clock_frequency: natural := 50e6;
			address: unsigned(6 downto 0) := b"0100110");
		port(
			clock: in std_logic;
			reset: in std_logic;
			scl: in std_logic;
			sda: inout std_logic;
			port0: inout unsigned(7 downto 0);
			port1: inout unsigned(7 downto 0));
	end component pca9555;

	signal reset: std_logic := '0';

	-- PCA9555 signals, GPIO board 0
	signal port0: unsigned(7 downto 0);
	signal port1: unsigned(7 downto 0);

	-- PCA9555 signals, GPIO board 1
	signal port2: unsigned(7 downto 0);
	signal port3: unsigned(7 downto 0);

begin

	pca9555_instance: pca9555
		generic map(
			clock_frequency => 50e6,
			address => b"0100110")
		port map(
			clock => clock_50mhz,
			reset => reset,
			scl => scl,
			sda => sda,
			port0 => port0,
			port1 => port1);

	port0 <= dip_switch & button;
	led <= port1;
	reset <= not neg_reset;

end architecture rtl;
